> What happens is this.. When a start-bit is detected, it will 
> start the FSM 
> (which i assume was in an IDLE state before this), and start 
> shifting the 
> bits into the receiver register.. But the baud_clk train 
> remains constant, 
> before and after the byte is moved in...
> 
> To me, that indicates a fixed sampling period.. whether they 
> use a single 
> point or multiple voting points, the period is still fixed.. 
> makes sense from 
> the designer's point of view... easy to implement, works as 
> long as users 
> stick to the standard baud rates, within a certain error margin..

I think you are a bit (baud?) confused. The FSM runs at a mutiple of the
baudrate, often 16 (sometimes 3, IIRC sometimes 64). So there is an
error (up to 1/16 of the bit cell) in where the FSM thinks the start of
the start bit and hence the centre of each bit cell is. This remains
constant for the entire character, and eats from the error budget. But
at the (first edge of the) start bit of the next character this error is
effectively reset, so it does not accumulate over characters. So this
error has nothing to do with how fast characters are send (in the sense
of line utilisation). (And neither does it depend on the baudrate.)

Wouter van Ooijen

-- -------------------------------------------
Van Ooijen Technische Informatica: www.voti.nl
consultancy, development, PICmicro products
docent Hogeschool van Utrecht: www.voti.nl/hvu
 

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