On Thursday 03 February 2005 17:25, Bob Axtell wrote:
> No, not quite right, Shawn. You are mixing up sample clock with the
> start of an individual
> serial frame.  But once you get this, you'll realize that asynch really
> does mean asynch

I know what you mean... but I don't think that I'm mixing it up... cause I've 
just read another one... from another EDA company..

This one says that their baud sample clock, is derived by continuously 
sampling the input signal... and mentions that the baud sample clock is 
adjusted to be in the middle of the bit.. And this one deliberately draws the 
baud sample clock with relation to the falling edge of the start bit.. the 
other one doesn't.. So, to me, this means that they will change their baud 
sample clock depending on when the start bit happens...

What i'm trying to say here is that not all UART are built the same... and not 
all are really asynchronous... some are pseudo-asynchronous...

BTW.. the sample clock that i've mentioned for all these examples is not the 
sampling clock... the sampling clocks are usually several times faster than 
the baud rate to sample each bit many times.. that's why i used the word baud 
sampling clock to imply that it only occurs once in a bit... the shift 
registers are shown to change content a little while after the baud sample 
clock pulses..

> My tests indicate that is a small delay is inserted between serial bytes 
> going out, an error of as much
> as 4% (+/- 4%) will usually still work.

My rule of thumb is 3%...

cheers...

-- 
with metta,
Shawn Tan

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