No, not quite right, Shawn. You are mixing up sample clock with the 
start of an individual
serial frame.  But once you get this, you'll realize that asynch really 
does mean asynch

The serial transmitter sends the first edge of a serial frame, which 
consists (usually) of a
START bit , 8 data bits, and a STOP bit. As soon as the START bit 
begins, from that point
on through the  frame until the end of the STOP bit, timing is precise. 
The receiver UART
locks on at the beginning of the START bit and subjects the remaining 
bits to a rigid timing
test until the end of the  STOP bit, then the UART is released from its 
rigid timing. The 8
data bits are extracted to do whatever needs to be done.

Now, the UART is released, looking for the leading edge of a START bit 
again. That leading edge
could begin as soon as the STOP bit ends, or it could begin a second 
later, a day later, or a fortnight
later. That's what is meant by asynch communication. Now it can be 
readily seen that if the
transmit bit width is slightly different to that expected by the 
receiver, the data can still be transferred
reliably, as long as a tiny delay is inserted between serial bytes 
(frames). That's all you need to do.

My tests indicate that is a small delay is inserted between serial bytes 
going out, an error of as much
as 4% (+/- 4%) will usually still work.

Make sense now?

--Bob

Shawn Tan Ser Ngiap wrote:

>>>of the start bit. The OP was talking about a UART that assumed the start
>>>bit at a fixed position relative to the previous character.
>>>
>>>Wouter van Ooijen
>>>      
>>>
>>Hmmm.....
>>
>>That is not how I read it.
>>    
>>
>
>I might be making a big mistake taking a dip into this again, but here goes... 
>I just read the data sheet for the plug-in IP from two major EDA companies... 
>This is what I gathered from reading it.. But since I do not have the IP in 
>hand, I cannot verify it.. If someone has it, maybe they can verify it..
>
>The sampling point baud signals (call it baud_clk) are divided from a main 
>clock... This results in a regular signal... Let's imagine a train of thin 
>square impulses...
>
>What happens is this.. When a start-bit is detected, it will start the FSM 
>(which i assume was in an IDLE state before this), and start shifting the 
>bits into the receiver register.. But the baud_clk train remains constant, 
>before and after the byte is moved in...
>
>To me, that indicates a fixed sampling period.. whether they use a single 
>point or multiple voting points, the period is still fixed.. makes sense from 
>the designer's point of view... easy to implement, works as long as users 
>stick to the standard baud rates, within a certain error margin..
>
>cheers..
>
>with metta,
>shawn tan.
>
>
>
>
>
>  
>


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