> > of the start bit. The OP was talking about a UART that assumed the start
> > bit at a fixed position relative to the previous character.
> >
> > Wouter van Ooijen
>
> Hmmm.....
>
> That is not how I read it.

I might be making a big mistake taking a dip into this again, but here goes... 
I just read the data sheet for the plug-in IP from two major EDA companies... 
This is what I gathered from reading it.. But since I do not have the IP in 
hand, I cannot verify it.. If someone has it, maybe they can verify it..

The sampling point baud signals (call it baud_clk) are divided from a main 
clock... This results in a regular signal... Let's imagine a train of thin 
square impulses...

What happens is this.. When a start-bit is detected, it will start the FSM 
(which i assume was in an IDLE state before this), and start shifting the 
bits into the receiver register.. But the baud_clk train remains constant, 
before and after the byte is moved in...

To me, that indicates a fixed sampling period.. whether they use a single 
point or multiple voting points, the period is still fixed.. makes sense from 
the designer's point of view... easy to implement, works as long as users 
stick to the standard baud rates, within a certain error margin..

cheers..

with metta,
shawn tan.





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