Jan-Erik Soderholm wrote:
> Bob Axtell wrote :

>>3. INT adds a lot of overhead. If all you need to do is set a 
>>few flags in global registers, there is no need to save W,
>>status, FSR, or PClath if all you need to do is set a few flags.

But the moment you have to move anything around (Rx characters)
you're forced to save and restore everything.

> 
> And, on the PIC18-line, that (saving of the "important" regs)
> is done on the fly without any extra cycles. So *very* short
> ISR's can be much faster on the 18's then on the 16's (if you
> need the context saving).
> 
> And, yes, this doesn't work well (or at all) if you use both
> interrupt priority levels, since there is only one set of
> shadow context registers... Well, you can't get everything,
> can you ? :-) :-)

Sure you can. Use a different processor family<G>.

So the 18's are only 'half baked' since they should have
had TWO sets of shadow context registers if there are two
levels of interrupt priority.

Wasn't it the TI TMS9900 that had a hardware register
which pointed to RAM where ALL the other registers were kept
as offsets from the base pointer.
Changing context meant adding or subtracting the register
count from the registers pointer. One could have multiple threaded
and reentrant code by simply managing the registers pointer.
I never programmed them but remember looking at them back
in the 80's and thinking, 'nice way to do it'.

Robert

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