Harold Hallikainen wrote:
> ACCESSBANK NAME=accessram  START=0x0            END=0x7F
> DATABANK   NAME=gpr0       START=0x80           END=0xFF
>
> SECTION NAME=access  RAM=accessram
>
> The linker complains:
>
> Error - section 'access' has a memory 'accessram' which is not defined
> in the linker command file.
>
>
> So... Linker Experts, what am I doing wrong?

I just replied to this saying you should make the names upper case.  I
remember a problem with the linker in that area.  After I sent that message
I thought to check my own linker scripts (Oh well, better late than never),
and found I use lower case names too.

On closer inspection, I'm not sure why it's complaining.  However, naming
the access bank "access" is a bad idea.  The UDATA_ACS directive defaults to
".udata_acs", so it is a good idea to use that name unless you are doing
something very special and understand exactly what is going on.  I've never
found such a case in the dozens of PIC projects I've done.

Here is my linker script for the 18F252:

//   Linker control file for the PIC 18F252 processor.
//
CODEPAGE NAME=config START=0x300000 END=0x30000D PROTECTED //processor
config words
CODEPAGE NAME=idlocs START=0x200000 END=0X200007 PROTECTED //ID words
CODEPAGE NAME=eedata START=0xF00000 END=0xF000FF PROTECTED //Initial EEPROM
data

CODEPAGE NAME=code0 START=0 END=0x7FFF //program memory

ACCESSBANK NAME=accessram START=0x0  END=0x7F PROTECTED //RAM part of access
bank

DATABANK NAME=bank0 START=0x080 END=0x0FF //register bank 0
DATABANK NAME=bank1 START=0x100 END=0x1FF //register bank 1
DATABANK NAME=bank2 START=0x200 END=0x2FF //register bank 2
DATABANK NAME=bank3 START=0x300 END=0x3FF //register bank 3
DATABANK NAME=bank4 START=0x400 END=0x4FF //register bank 4
DATABANK NAME=bank5 START=0x500 END=0x5FF //register bank 5

SECTION NAME=.udata_acs RAM=accessram //bank 0 part of the access bank
SECTION NAME=.BANK0 RAM=bank0 //for registers explicitly in bank 0
SECTION NAME=.BANK1 RAM=bank1 //for registers explicitly in bank 1
SECTION NAME=.BANK2 RAM=bank2 //for registers explicitly in bank 2
SECTION NAME=.BANK3 RAM=bank3 //for registers explicitly in bank 3
SECTION NAME=.BANK4 RAM=bank4 //for registers explicitly in bank 4
SECTION NAME=.BANK5 RAM=bank5 //for registers explicitly in bank 5

SECTION NAME=.OVR1_B0  RAM=bank0     //for overlays in bank 0
SECTION NAME=.OVR2_B0  RAM=bank0     //for overlays in bank 0
SECTION NAME=.OVR1_B1  RAM=bank1     //for overlays in bank 1
SECTION NAME=.OVR2_B1  RAM=bank1     //for overlays in bank 1
SECTION NAME=.OVR1_B2  RAM=bank2     //for overlays in bank 2
SECTION NAME=.OVR2_B2  RAM=bank2     //for overlays in bank 2
SECTION NAME=.OVR1_B3  RAM=bank3     //for overlays in bank 3
SECTION NAME=.OVR2_B3  RAM=bank3     //for overlays in bank 3
SECTION NAME=.OVR1_B4  RAM=bank4     //for overlays in bank 4
SECTION NAME=.OVR2_B4  RAM=bank4     //for overlays in bank 4
SECTION NAME=.OVR1_B5  RAM=bank5     //for overlays in bank 5
SECTION NAME=.OVR2_B5  RAM=bank5     //for overlays in bank 5

SECTION NAME=.EEDATA   ROM=eedata    //initial EEPROM data


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