the general idea would be that you have a start and end position in ram, assume for a moment that in the datalogger application you go around on a regular basis and copy data to a laptop or similar. collection can start from scratch. as long as no power outage occurs one can keep track of live data with just the two pointers in ram , reusing all cells equal (except for the two cels you use as backup locations when there is a power failure. In case of power failure you know a couple ms ahead of time you finish any pending logging operations , copy pointers from ram to eeprom and wait for power to come up after it went down , you copy the pointers back from eeprom to ram and go back to business Prediction of power outage is simple put diode in series with supply, a cap on the ouput to ground (supercap would work nice) measure voltage from supply line (before the diode) with comparator input and resistors. Peter ----- Original Message ----- From: "Jake Anderson" To: "Microcontroller discussion list - Public." Sent: Monday, December 06, 2004 12:07 AM Subject: RE: [EE] EEPROM address storing/ write equalisation > my question with EEPROM load leveling with a circular write pattern is > how do you know where you were pointing to without also writing that to > eeprom in a paticular location? > > >> -----Original Message----- >> From: piclist-bounces@mit.edu [mailto:piclist-bounces@mit.edu]On Behalf >> Of Denny Esterline >> Sent: Monday, December 06, 2004 14:46 >> To: Microcontroller discussion list - Public. >> Subject: Re: [EE] EEPROM address storing >> >> >> >> > Another way to do this >> > Select one eeprom cel for a counter BUT make sure you detect power >> failure >> > before power goes down (need enough backup power from a capacitor or >> battery >> > to complete write operation). You would only write to the counter if >> power >> > is going to fail. >> > >> > Better yet, to insure equal wear on all eeprom cels store circular and >> use a >> > start and end location. >> > >> > Peter >> > >> >> Detecting power down is an interesting idea I hadn't considered. Probably >> have to add some additional hardware to sense the voltage level - any >> good >> suggestions for that? >> >> Best I could think of is a diode and cap in series across the power rail >> and a comparator between the cap and the V+ rail. When V+ falls below the >> cap voltage (one diode drop below the previous V+) the comparator could >> trip an interrupt. Hmm... might need a bleed resistor across the cap to >> make sure it doesn't cause a false interrupt on power up. >> Probably even get >> by with one of the internal comparators. >> >> -Denny >> >> >> _______________________________________________ >> http://www.piclist.com PIC/SX FAQ & list archive >> View/change your membership options at >> http://mailman.mit.edu/mailman/listinfo/piclist > > _______________________________________________ > http://www.piclist.com PIC/SX FAQ & list archive > View/change your membership options at > http://mailman.mit.edu/mailman/listinfo/piclist > _______________________________________________ http://www.piclist.com PIC/SX FAQ & list archive View/change your membership options at http://mailman.mit.edu/mailman/listinfo/piclist