Marcel Duchamp wrote:
> The uart drove the ISR.  The ISR stuck bytes in buffers and set flags to
> say "buffer #1 full", "now using buffer #2", etc.
>
> The main loop was short and tight reading flags.  When the flags said a
> buffer was full, it was written out to the card; meanwhile, the uart was
> pumping data into the second buffer.  Buffers were both 512 bytes.

This works, but is wasteful of buffer space and more complex than necessary.
I assume that you can load bytes onto the flash card quickly, but then
writing a loaded buffer into the flash is where the delay is.  In that case,
you only need a single FIFO.  It gets drained as fast as bytes are stuffed
into it when loading the flash buffer.  In other words, it's empty during
that time.  The real purpose of the buffer is to have some place to put new
bytes while the flash is busy doing a write.

Your system only allows 512 new bytes to come in during a flash write,
although twice that much RAM is actually used.  Since your system works, it
proves a single 512 byte FIFO is all that is required, probably less if you
did the math.  As Bob Ammerman already pointed out, the buffer size depends
on the incoming data write times the flash write time plus a little extra.


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