On Sat, 6 Nov 2004, Russell McMahon wrote:

>
> What's the feeling about using the PIC10F,and other processors which do not
> have antibrownout circuitry,in real world situations.
>
> I have a present problem where a new batch number of processors (Zilog)
> often fail to start cleanly because they latchup if you brownnout the supply
> and then recover it. They then must have Vdd taken to hard ground for about
> one second before they will work. Unless the processor is guaranteed to work
> under such situations you are left with a product that may hand fatally on
> eg noise spikes. What do people do?

What I've done so far:

- use a parallel regulator whenever the power budget permits. Can be 
zener, TL431 based, or more complex. This makes for low power system 
impedance down to dc and discourages spikes (both positive and negative).

- use a leak resistor, usually 1k or 470r, across the cpu power rails, 
again when power budget permits. Then the device can be powered down and 
up again rapidly (without this the power rail will not go close enough to 
gnd to reset cleanly after a latchup).

- decouple sensitive pins (like reset MCLR on pic) to the rail they are 
referenced to. For pic this is Vdd (reset occurs when MCLR goes 0.4V under 
Vdd afair - this is by far the lowest noise margin on the chip, excepting 
ad inputs and grounding for analog grounds in ad and comparator work). 
Because of the reset polarity I have to use a small value capacitor 
(usually under 1nF), so it won't fight the reset cap and ICSP circuitry. 
The normal reset circuitry is connected through a small series resistor 
(usually 100R or 47R).

- use a switch-all power circuit. This means, cpu power is either good, 
and thus on, or not good, and thus off. A simple device that implements 
this is a 555, a zener, a resistor and a capacitor, unfortunately the 
output voltage drops easily under load. The 555 output is used directly to 
power the cpu. A switch-all power circuit can be implemented easily around 
a discrete Schmitt circuit. By the way the 555 is a pretty good reset chip 
imho ;-)

- more complex circuits, like old MCS51 based computers used elaborate 
state machines to drive reset, using several LS TTL and opamp packages.

I think that there is no perfect solution, since a certain probability ca 
be associated to each type of reset circuit, where it will fail. I also 
think that manufacturers who make chips that are prone to latchup within 
their power supply and clock frequency range are neglecting something 
important. How hard can it be to audit the design and make sure all state 
machines have a reset feed, and that undesirable charge buckets in the 
silicon are provided with draining arrangements.

I have had my fair share of problems with this (with pics too), and I have 
strong opinions on the matter (especially since I know that some 
manufacturers make stable chips and others don't seem to care). But I am 
open to suggestions.

Peter

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