Dave VanHorn wrote :

> > There is a difference between 'interrupt latency' and the 
> > overhead for 
> > entering the interrupt handler. The extra instruction 
> > cycle(s) are due to 
> > a synchronizing flip-flop on the interrupt source.
> 
> It's the overhead, that I'm wondering about.
> 
> Basically, I'm wondering if they are storing these registers 
> in paralell, or series, and just "hiding" that activity from you.

You are talking about the three "shadow" registers that holds
the values of W, STATUS and BSR during the interrupt, right ?
(In the data sheets they are called WS, STATUSS and BSRS, but
they are not normal SFRs or memory mapped, so you can not "see" them.)

You could call it "hiding", since it's done behind the curtains.
There are no additional cycles wasted, the interrupt as such
takes as much time as it does on the PIC16, but there you have
to save those regs yourself and *that* will take a number of
cycles.

The net effect is that interrupts on the PIC18's are faster then
on the PIC16's (in general). If it's a very short ISR, the difference
could be significant.

Note also that you do not have the option to *not* save them.
You *do* have the option to *not* restore them (see description
of RETFIE), but that will not save any cycles anyway...

Regards,
Jan-Erik.
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