At 03:06 PM 10/15/2004, Jan-Erik Soderholm wrote:

>Dave VanHorn wrote :
>
> > How many clock cycles does it take to save them?
>
>The saving and restoring of WREG, STATUS and BSR on the
>"fast return stack" are made on the fly and is transparent
>to the application ("no extra cycles", didn't I say that ?).

Well, I'm still fuzzy. From the finish of the last instruction, to the 
start of the first instruction of the ISR, how many xtal clocks happen?

>Now, *if* you use priority interrupts (high/low int), this doesn't
>realy work, since the fast return stack is just one level...

Hmm.

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