Hi Bob,

> > I vote for the yahoo group (as much as I hate them), since this isn't
> > relevant to pic discussion.

    It is already there and we already have 27 member signed in for it ! The
homepage is http://groups.yahoo.com/group/MultiAnalyser/

> 7. Front end improvements: AC/DC coupling. Input amplifier and attenuator
> for 1-2-5 steps.

    That helps a lot, it is one of the annoying things of the Bitscope. The
weird attenuator values.

> 8. More advanced triggering for the logic analyzer: at least 2 stages with
> don't cares for each stage.

    That is essencial. I have a logic analyser that just triggers in one
stage and it is almost impossible to use for many tasks. Another important
thing on the logic analyser side is the clock generator. It has to be
flexible to accomodate the different uses and external clock is also a nice
thing to have if we go the FPGA way...

Best regards,
Alexandre Guimaraes


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