On Thu, 16 Sep 2004, Herbert Graf wrote:

> On Thu, 2004-09-16 at 14:15, Philip Pemberton wrote:
>> That's effectively what I'm doing now - grabbing 1024 bytes, blasting them to
>> the host, then grabbing another 1024 bytes (8 rows). I haven't tried doing
>> the imaging cycle like that, though. I'll have to try that :)
>>
>> The other option, of course, is to hook up a 16k RAM (62128?) and a pair of
>> 4040 counters - use one 8-bit port to read/write the data lines, then use
>> another five I/O lines to run /CS, /RD, /WR, COUNTER_CLK and COUNTER_RST.
>> Blast the data into the RAM (framebuffer), then come back and read it out
>> later.
>
> This sounds like something that a CPLD would be perfect for. Let the
> CPLD generate the addresses and write pulses for the SRAM. Have a look
> at my logic analyzer project:

Or an FPGA as I mention....especially as devices like Altera's Cyclone are 
so versatile and cheap now, seem pointless to use a CPLD when you can use 
an FPGA that costs the same as a PIC ;-)

-marc
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