> >> As someone else has mentioned, the baud rate is irrelevant, the above
> problem is just as bad at 300 baud and 19200 baud<<
>
> Why would that be?  Aren't serial bitwidths wider at lower speeds?   Just
> curious - trying to get an educashun.

Each bit is a certain percentage of the total frame period. The timing is
synchronised by the start of the start bit and then must stay in sync for
one data word. At any data rate, if you move more than a certain percentage
of word length from the centre of a bit then you cross a bit edge. In one
direction you sample the bit before the one you ought and in the other
direction you sample the bit after the one you ought. In either case the
error is ABOUT 5%. This applies at whatever speed you are working.

eg with an N81 data signal there is 1 start bit, 8 data bits and 1 stop bit.
Assume the transmitter is perfect and the receiver clock is fast.
The receiver will sample each bit progressively earlier.
The timing starts at the start of the start bit (say that 10 times rapidly)
and ends when the stop bit is sampled.
This period OUGHT to be 1 + 8 + 1/2 = 9.5 bits from the start of start to
the middle of stop.
The fastest sampling allowed is if the stop sample JUST is inside the stop
bit rather than inside the preceding data bit. This is 9 bit times from the
start of start. The clock would be running 9.5/9 = 1.0555r or 5.56% fast for
this to happen, regardless of baud rate. If you ASSUME the stop bit is
correct and only worry about sampling the data bits then you can be 8.5/8 =
6.25% fast. Student is left to work out how slow you can be.

Note that this 5 % or 6 % error can be spread between transmit and receive.
IF they both drift the same way with eg temperature the result MAY be better
than if one end is crystal controlled. This depends on drift matching and on
similar temperature environments at each end.
As a general rule, if one end is crystal controlled then you can allow about
5%clock error at the other end before bit errors occur. YMMV.

        RM

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