Is it just me, or does that waveform look odd? The high time is 10x the low
time... To me, it seems like the low time should be slightly longer than the
high time.

Are you sure you are executing the statements below, or that your pins are
configured like you think they are?

Another possibility is that the OUT0 followed immediately by the IN0 is
causing problems, perhaps some wierd hazard in the chip.

Did you try this just writing the values, as opposed to doing the and/or
thing? ie,

while(1) {
  PC_DR = (char) 0x80;
  PC_DR = (char) 0;
}

Another thing to try would be to unroll about 20 of these and see what it
looks like:

while(1) {
 PC_DR |= (char) 0x80;
 PC_DR &= (char) ~0x80;
 PC_DR |= (char) 0x80;
 PC_DR &= (char) ~0x80;
 PC_DR |= (char) 0x80;
 PC_DR &= (char) ~0x80;
 PC_DR |= (char) 0x80;
 PC_DR &= (char) ~0x80;
...
}

You could set another pin the first time to trigger on if you have a two
channel scope.

Regards,
 Bob Monsen

----- Original Message -----
From: "Herbert Graf" <mailinglist2@FARCITE.NET>
To: <PICLIST@MITVMA.MIT.EDU>
Sent: Sunday, August 22, 2004 1:59 PM
Subject: Re: [EE:] Zilog Circuit Cellar Kit


> On Sat, 2004-08-21 at 02:54, Bob Barr wrote:
> > You don't need to execute very many multi-cycle instructions to burn
> > 200 clock cycles.
> >
> > Figuring timing budgets on a Z80 can be a real eye-opener.
>
> It would appear so. Thanks to all for the help. I have condensed my
> results so perhaps somebody here will be able to tell me with certainty
> if this is the best I can expect.
>
> I have the following code:
>
> while (1)
> {
>         PC_DR |= (char)0x80;    // MCLK high
>
>         PC_DR &= (char)0x7f;    // MCLK low
> }
>
> Which compiles to this:
>
> 53                              while (1)
> 0000A9                     A   134    L_12:
>                            A   135    ;   54                            {
>                            A   136    ;   55
PC_DR |= (char)0x80;    //
> MCLK high
> 0000A9 ED389E              A   137      IN0     A,(158)
> 0000AC CBFF                A   138      SET     7,A
> 0000AE ED399E              A   139      OUT0    (158),A
>
> 61                              PC_DR &= (char)0x7f;    // MCLK low
> 0000B1 ED389E              A   146      IN0     A,(158)
> 0000B4 CBBF                A   147      RES     7,A
> 0000B6 ED399E              A   148      OUT0    (158),A
>
> 0000B9 C3 A9 00 00         A   154      JMP     L_12
>
> Which looks reasonable to me, yet when I put a scope on the pin I get a
> 50kHz signal (please see attached image).
>
> Does this seem at all reasonable to anyone?
>
> I see nothing in the assembly that would take ANYWHERE near as long as
> that, could the IO accesses REALLY be burning that many clock cycles? I
> don't know how many cycles the JMP L_12 takes, but I can't imagine it's
> in the hundreds.
>
> FWIW the dev kit is SUPPOSED to run at 50MHz, so I'm seeing 1000 clock
> cycles needed to execute the above code.
>
> I REALLY hope I'm doing something wrong, otherwise this contest entry
> will be academic at best, I'll probably enter with a piss poor slow
> thing, and then rewrite everything for a PIC or AVR with a support CPLD
> to make things easier on me...
>
> Thanks again to all for your help. TTYL
>
>
>
>
> -----------------------------
> Herbert's PIC Stuff:
> http://repatch.dyndns.org:8383/pic_stuff/
>
> --
> http://www.piclist.com#nomail Going offline? Don't AutoReply us!
> email listserv@mitvma.mit.edu with SET PICList DIGEST in the body
>
>
>


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