Typically on our boards...ranging from 2 to 16 layers, we simply drop a via
to the plane from the cap.  IF you can place the cap where it can tie
directly to the pins, its better of course.  The amount of capacitance and
number of layers also affect it, and at what speed the chip is running.
There are points where the inductance of the trace will nullify the effects
of the caps.  In our case,
the major ASIC's will have multiple types and numbers of caps, ranging from
.001uF to 10uF.

Xilinx has some good info (I have mine from a seminar) but it might be on
thier website as well in analyzing the effects of caps, frequencies and
layout issues.

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