On Fri, 9 Jul 2004 21:36:43 +1200, you wrote:

>[EE:] Design Challenge - Lowest cost PWM
>
>Roman Black where are you ... ? :-)
>
>APPLICATION:
>
>I have had and have ongoing needs to PWM modulate FETs at supersonic
>frequencies - typically I use 20kHz to 25 kHz as this generally produces
>inaudible results. Aim may be considered to be load control of various
>loads. May be motors or resistive or reactive loads. Lower frequency PWM=
 is
>unacceptable either due to audible noise or the ability for frequency to=
 be
>detected in some way. Specifics unimportant to this challenge.  DO NOT
>address how to make low frequency better - this is not what the =
challenge is
>about.
>Objective:
>
>
>1.    Produce hardware PWM variable from 0 to 100% at at least 20 kHz.
>
>2.    Input to be an analog voltage SOMEWHERE in the 0 to 5 volt range. =
eg
>may be 0 - 3 or 2.3 - 4.2 or whatever. Circuit needs to be able to be
>designed to accommodate any such given voltage at construction time. eg =
use
>of designed fixed resistors OK. (Ability to accept eg binary word or =
lower
>frequency PWM signal as input may be acceptable)(Resolution should be at
>least 6 bits or equivalent and more is better). Input signal is =
essentially
>DC - ie may change in steps up to a few times per second.
>
>3.    Linearity and accuracy not overly crucial but the better the =
better.
>eg 1% excellent, 5% OK, 10% is rather marginal .
>
>4.    PWM waveform shape is not crucial but the sharper the rise and =
fall
>edges the better.
>
>5    Sensitivity to component values included in 3.
>
>6.    Assessment of all up cost is informal. eg includes components, =
board
>area and assembly costs but no formula is proposed for these. =
Construction
>would probably be single sided with links as requisite. Machine assembly
>with manual backup as required. Assembled in PRC - labour is cheap!
>
>7.    Target volumes are low to moderate production - say 100s to 10,000
>range but one off amateur applications may benefit from this.
>
>8    Frequency of PWM is not too critical. eg 22 to 28 kHz would be OK =
for a
>nominal 25 kHz design. .
>
>It is appreciated that resolution, accuracy, linearity and other terms
>overlap somewhat in this application. The idea should be clear enough
>without tighter definition or specification.

ATTiny13 would seem a good fit - internal RC osc, on-chip ADC,  internal =
RC at up to 9.6MHZ
you could get about 0.1uS PWM resolution in software, so about 0.2% =
resolution at 20KHz

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