"Peter L. Peres" wrote:
>
> The attached pdf illustrates the problem of 'just using pullups' wrt.

Of -course- there is leakage current through the unpowered device.
In fact the bulk diode is trying to power the whole unpowered
system so it will be pulling hard against  the entire Vdd load,
not just leakage. That is the reason you have to disconnect the
unpowered side of the bus even though it is open drain.

I have a kluged system with two different power sources, and the
SPI data and clock lines are able to power the PIC side
unintentionally through the bulk diodes. Fortunately the PIC side
only needs milliamp or so so no harm done (but it's getting redesigned).

> leakage current. The capcitor Jinx wants to use may do the trick.

As currently proposed, I don't see how that will help anything.
Please explain.

If anything the capacitor will make the I2C bus see a
transient low as the cap keeps the 4066 turned on while
PIC VCC dies since the cap will only be discharged through the
10k pullup (now pulldown) since the 4066 gate has 10^^12 ohms
input resistance.
This R/C  tau will be significantly longer than the power Vdd
drop if nF are used.

If one wants to use Jinx's design for delayed gate turn on,
they should add a reverse biased diode to PIC Vdd so
that the cap gets quickly discharged when Vdd drops.

This also illustrates why one should have pullups or pulldowns
on ALL PIC pins to keep your circuit safe while the PIC
initializes it's ports with the correct levels and direction
(always set levels BEFORE enabling outputs).

Better yet, use your LVD (or /MCLR) reset line so that the 4066
gate is disabled before PIC Vdd completely fails. There is usually
enough Vcc capacitance to hold up the rail for a few milliseconds
as power fails.

Systems where power fail detect is important use an isolation
diode on the input supply so a power fail detect device can
pull an interrupt low (high) well before Vdd even moves,
giving the processor time to shut down safely.
By sensing power fail BEFORE the regulator, you gain many
10s of ms to do your shut down housekeeping. An opto driven by
the raw input supply (battery or bridge) can provide
detection of input power loss while the power supply capacitors
keep the rail up long enough for a graceful shutdown.

Have fun working out the kinks...
Robert

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