>> What does the PCF8593 datasheet say about quiescent current
>> in I2C start condition ?
>
>I don't believe it says anything. There are 3 current specs in the d/s
>
>Operating - 200uA max
>I2C bus inactive - 15uA max
>Input leakage - +/- 1uA

That would be 'everything'. It means if SCL goes down after SDA the chip
will have 10x quiescent current from its backup source.

>I'm spending some time today making up a proper ground plane
>PCB to (a) make sure the clock is stable/reliable and (b) try out
>different switching arrangements (if necessary) of the pullups, so
>I'll have to get back to you about that

The more I think about this the more I believe there is a problem here.
The simplest pullup switch would be a PN2222 with base to the power
monitor of the PIC (high = operating, low = reset), collector to pic +Vdd
and emitter to SCL pullup resistor. There would also be a pulldown on SCL
and SDA, both 500k-1meg. SDA pullup would also be powered by the PIC Vdd.

There could also be a problem with the SDA and SCL voltages floating in
the 'forbidden' voltage area of the PCF input buffers (which would cause
said buffers to drain extra power from the PCF backup system). Is that 1uA
leakage guaranteed over input voltage range or at Vil and Vih only ? Are
the PCF inputs specified as Schmitts ? (I don't think so). If they are
Schmitts then this problem may not exist (unless they are pre-buffered
Schmitts).

Peter

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