Ken Pergola wrote: > Robert Rolf wrote: > > I had written up a detailed critique of your schematic... > Since you've already spent the time, I would like to see your critique in > the spirit of learning and adding to this thread (as long as it's > constructive criticism and does not put anyone on the spot or make them feel > bad, and I'm not implying that you will). Real-time clocks are fun and > design reviews are a good learning experience. You asked. How 'constructive' this will be is a matter of interpretation and the mood of the recipient. Jinx wrote: > > I'll say it again. > > Pullups/pulldowns DON'T DRAW ANY POWER if they are NOT > > pulling against anything > > Yes, of course. I realise that and that's why the discussion about > how to disconnect them so that they aren't either connected to a > dead PIC or being a burden on the back-up battery/cap Is the PCF driving the I2C bus when power failed? If it isn't (why would it, it's a slave) then you have no reason to disconnect the I2C pullups. The power failed PIC is the chip needing the 1M pulldowns. {And since there is no power draw, the pullups can be as 'stiff' as you need them to be for your bus loading, within the limits of the on resistance of the 4066. You can also distribute the pullup value between the PCF and the PIC side if need be. e.g. 100k on the PCF, 2k2 on the PIC and other high speed stuff. > This is a circuit I've just made Reasonable but I have some questions and criticisms. Why does the xtal trimcap go to Vcc rather than ground? Vcc is much more noisy than grounds (usually) so you end up coupling noise into the crystal, jittering the clock, giving timing errors in the long term (if that wasn't an issue why the trimmer?) And most trim's I've seen for 32khz xtals are across the xtal. (Dallas 1302 for example). What is the width of the /int pulse? Why are you not disconnecting it with one of the 4066 gates? Using a larger value pullup would reduce your standby current draw, but since it's an output you can put the pullup on the PIC side of the 4066 and have NO periodic current increase from the 1 Hz int. NiCads are lousy batteries for backups since their self leakage is high. A diode connected 3V lithium would give you 10 year shelf life. Ni-Cads are lucky to give you 3 months (just look at your old 486 motherboard to see your dead nicad). Why are you not using a 4066 which has a much lower on resistance? Why are you disconnecting the pullups when there is no need to do so (per my reapeated comments on this point)? Why pulldown the I2C inputs when the idle state of the bus is high? http://www.ibilce.unesp.br/courseware/i8051/i2c_1.htm " I2C Bus Idle State Both data and clock lines are HIGH when the bus is not busy." You just run the risk of creating a false start state or otherwise erroneous states. You certainly do NOT want to load the data line with nF worth of capacitance since that reduces your noise margins. You don't need the cap to control slope if you leave the pullups connected to the PCF chip. You don't need the 1M Pic Vcc pulldown since the PIC chip will do that for you (to about 0.6V). > I2C still works (I have the PIC reading the PCF8593 and updating > an LCD every 0.2s) I am surprised that is works if you really have nF cap on the SDA line. And you have about twice as many passives as you need. You also don't show how you're driving the 4016 gate since you want it to go low well before the PIC pulls down the control lines. Presumably you are tying it to /MCLR which is driven by your LVD (low voltage detect) (but with resistor diode clamp isolation should you be doing ICSP, where /mclr goes to 12V. > With the PIC turned off, consumption is 7uA (excellent, I can What is the PCF spec? You should be able to get below that. With a Dallas 1302 my standby (3v) is so low I can't measure it reliably with my Fluke 87 (certainly less than 0.5 uA when looking at the voltage drop across a 1k measurement resistor). > certainly live with that), rising to 50% duty cycle ~50uA if INT > is active (1Hz INT activity shows that the IC is still running) So make the 100k /INT pullup much larger. Or disconnect it since the PIC can't doing anything with the pulse when it is unpowered. > The ?nF can be installed to introduce a delay and so turn SDA > after SCL. I'll have to read up on that You DO NOT NEED OR WANT IT. Delay the 4066 gate pullup to Vcc (enable delay) with that cap instead, ensuring that the PIC is alive and well before connecting the PDF to the bus. > This by no means a final circuit, but as it appears to have worked I hope not. It has many flaws. > straight out of box I can leave it alone for a day or two while I get > back to the w My advice is worth exactly what you paid for it. Should you find that you use it, contact me off list for royalty info . Robert -- http://www.piclist.com hint: PICList Posts must start with ONE topic: [PIC]:,[SX]:,[AVR]: ->uP ONLY! [EE]:,[OT]: ->Other [BUY]:,[AD]: ->Ads