>-----Original Message-----
>From: Jinx [mailto:joecolquitt@CLEAR.NET.NZ]
>Sent: 25 June 2004 12:32
>To: PICLIST@MITVMA.MIT.EDU
>Subject: [PIC:] MSSP module
>
>         bcf     pir1,sspif
>         mov     0x55,sspbuf   ;send data
>         btfsc   pir1,sspstat,r_w
>         bra     $-2
>
>         bcf     pir1,sspif     ;wait for ACK
>         btfss   pir1,sspif
>         bra     $-2
>

I'm a little surprised that this works.  The SSPIF bit gets set at the same
time that RW gets cleared, which is on the falling edge of the acknowledge
clock pulse.  Unless I have missed something, you are clearing SSPIF
directly after it has been set, and are then waiting for it to be set again.

Regards.

Mike




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