I am trying to build a motor controller to drive a robot from a PIC using an H-bridge, so I'm
reading up on FETs now in The Art of Electronics.  They have a circuit which limits the current
draw through a mosfet, which I'm trying to understand.

It's Figure 3.72c, with a PNP transistor before the source of the FET with a 0.5 ohm resistor from
emitter to base with the base wired to the source, and a 100k resistor from their +12V source to
the collector of the PNP and also to the gate of the MOSFET.    Originally when I was looking at
this circuit I thought the purpose of the transistor was to shut off when the voltage drop across
the 0.5 ohm resistor became more than 0.6V so that the gate was too far below the emitter.  But I
can't understand why this would stop the load from being powered.  It seems the voltage drop
across the 0.5 ohm resistor would lower the source voltage of the FET anyway, causing it to supply
less and less current.  The explanation for the circuit is left to the reader as exercise 3.21..
maybe I should try and find a copy of the answers somewhere.

If anyone has any insight, I would appreciate it, I think it would help out my understanding of
these transistors which I can't seem to wrap my head around.

Mark

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