On Mon, 2004-06-21 at 01:47, Matthew Brush wrote:
> 1. I am using a 1MB 1Mx9 70ns module (3 chips on the
> pcb, not the same chips, maybe a parity dealy or
> something).

        They are parity. Two of the chips are 4 bits wide and one of the chips
is one bit wide, hence the X9.

> So, I don't need the Address lines A10 &
> A11 correct, just A0-A9?

        Depends on your chips, I don't know the calculation offhand for how
many rows and how many columns equals what bit density. I'd start by
getting a datasheet for the chips on your SIMM. If you can't find one
then get a datasheet for a similar chip.

> 2. Can I think of the rows and addresses as:  Each of
> the rows as a byte and each column as a bit of that
> byte?

        Nope. Think of it as it is: a two dimensional array. Each combination
of row and address selects one set of 9 bits (in your case).

One easy way to look at things and ignore the row column aspect is to
combine the row and address into one number, counting becomes a little
weird, but if you're doing IDE you're used to this sort of thing (CHS is
the same sort of weirdness).

> 3. Does a refresh cycle simply consist of addressing
> each row & column at specific time intervals?  So, I
> could just use a timer interrupt on a PIC which just
> runs though all the possible row/column combinations
> every few mS or something?

        I think that would work, I'm much more familiar with DDR RAM, but I
figure the refresh cycles are similar (I think with DDR you don't need
to supply the row and column for refresh, it has it's own counter).
Again, get a datasheet, it will make all much clearly.

Note: the minimum refresh time, in my experience, has a LARGE margin
associated with it, so if this is a personal project and you're on the
end of doing enough refreshes I wouldn't worry about it (I've had DDR
chips running at refresh rates FAR below minimum and they still worked
without corruption.

> 4. I believe my SIMM has parity, does that mean I have
> to implement this, or can I just ignore the parity
> in/out lines?  I assume that the parity bit can be
> used as another data lines or something (hence the
> 1Mx9 instead of x8) ... correct?

        Parity just means 9 data lines. A non parity SIMM will still have the
9th parity line, it just won't be connected to anything.

> P.S. If anyone cares, my intended application will use
> a 16F877A as a DRAM controller which will be connected
> to rest of the project via it's PSP port and it will
> provide a simple interface to the DRAM.  There will be
> another 16F877A doing some other stuff on the PSP bus
> (IDE, parallel port).  I need to use up some samples
> :)
>
> Also, I will be more than happy to share my source
> code when I'm done if anyone is interested.

        Excellent! I already have a project in mind that could benefit from
this! :) TTYL


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