On Tue, Jun 15, 2004 at 12:16:33PM -0400, Matthew Brush wrote:
> Thanks for the info.
>
> I don't need to make the bus tri-state since all data
> will be latched or not latched into the devices only
> when I asked ... right?

Probably. Usually on a RAM the output buffers are only enabled when
CS, OE, and Read are all selected. So it is possible to ground OE and
only use CE to select.

BAJ
>
> Thanks
>
>
>
> > That's not difficult. It might be more difficult
> > finding
> > them. DigiKey and Mouser never seem to have the size
> > I
> > want in stock. Any of the parallel RAM chips you can
> > find/salvage should be useable. You might have
> > better
> > luck at jameco if you want a small quantity of DIP
> > versions.
> >
> > most of the SRAM chips have parallel address and
> > data
> > lines. To control, there is typically a /CE (chip
> > enable)
> > and a /WE (write enable). Some also have /OE (output
> > enable - used to tristate the data lines for bus
> > systems)
> >
> > If you're wanting to put it on the IDE bus, you
> > probably
> > want a version that has the /OE signal such as
> > CY62256.
> > It's rather large for only using 512 bytes, but it's
> > typical of the interface used by other chips.
> >
> > hope that gets you started in the right direction.
>
> =====
> MJ Brush
> LeftClick.ca Internet Media Services
> mbrush@[NOSPAM]leftclick.ca
>
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