from what little i've seen, 5-10 mills on each side (10-20 mills total)
around the maximum lead size is the "normal" range for ic leads.  for
surface mount discretes often longer is preferred, though again you
don't want those big pretty fillets.  of course your need to run traces
between pins and soldermask limitations also influence things.

of course as with all things, a web search may or may not help/overload
you depending on how you phrase the query.  i tried that and found the
ipc site which does have many common outlines and variations from some
manufacturers for specific parts in common cases, i.e. they've submitted
one for a specific part/package but the pattern is probably good for all
devices in that package.  it does take a little poking around on the ipc
site, but at least there's some reason to suspect they are good ones.

on the other hand, as i mentioned i finally just used what came with the
board package even though they were somewhat oversized pads, but since
i'll be doing hand assembly i figured that would make it easier and
would definitely work, where as small pads could have been a problem for
hand assembly, so assembly method doubtless has an impact as well (and
since i'm getting 56 of these tiny boards on a panel i definitely needed
them to be usable, even if not "ideal").

the company that will be making your board and their capabilities
definitely impact on what is the "best" layout, especially when they
don't do really fine work and you are using surface mount chips.  i used
olimex, their trace/space and drill size limitations definitely
complicated things but the price was right.  for a larger board with
many surface mount parts (that i didn't need to panelize) i'd probably
pay the extra for finer lines, smaller vias, and easier layout.


PicDude wrote:
>
> Not always, but sometimes.  If you can find an SOIC datasheet with the package
> dimensions and PCB layout, then use that as a guide and adjust accordingly
> for the Cerpak with the diff dimensions.  You'll have a decent idea of how mu
> pad you need around each pin, especially since the pin pitch is the same on
> both packages (0.050" IIRC).
>
> If not, use the SOIC pad layout for some other part in Eagle and the datasheet
> for that part as a starting point, and then adjust accordingly for the
> Cerpak.
--------

--
http://www.piclist.com hint: PICList Posts must start with ONE topic:
[PIC]:,[SX]:,[AVR]: ->uP ONLY! [EE]:,[OT]: ->Other [BUY]:,[AD]: ->Ads