Thanks Ken, for a very informative post.

I have also discovered that the SCK pin (16F876 0004 d/c) is VERY
sensitive to  loading. In spite of the 20mA output spec, if SCK
has more than a few 100pf on it, the SPI will only provide 7 or
fewer data and clock bits.
If found this out the hard way with a diode coupled 470pf
R/C delay circuit that simply would not work (too few bits
would come out).
Eventually I spotted very high frequency trash on the rising edge
of the SCK line as it passed through the HCMOS threshold.
Evidently the internal shift register/counter is driven
UNBUFFERED by the pin, so external capacitance slows the
clock edge sufficiently to cause problems. Adding an external
buffer solved the problem.

Robert

Ken Pergola wrote:
>
> Or rather:
>
> The SPI That Fooled Me
> ----------------------
>
> I just posted this message on the Microchip Forums, but I thought I'd share
> this with all of you on the PICList as well. If my mistake can help others,
> heck, it will be worth it (I'm sure it's not new to many of you, but for
> some people it may not be):

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