Yes a read or write will reset the latches, but it doesnt matter if the latches are reset after GPIF is set. I think the problem with the GPIF not getting set (not interupting) is when there is a read involved. I think you can write to it all day long and it will always interupt properly. Quote from the 12f manual: "If a change on the I/O pin should occur when the read operation is being executed (start of the Q2 cycle), then the GPIF interrupt flag may not get set. " It specifically mentions the Q2 cycle. Quote from the mid-range manual: "Q1: Instruction Decode Cycle or forced No operation Q2: Instruction Read Data Cycle or No operation Q3: Process the Data Q4: Instruction Write Data Cycle or No operation " So to me this looks like the bug is only in the Q2 read cycle, and does not affect the write cycle. I could be doing something terribly evil, but I have several prototypes that do a lot of constant writing to GPIO and still rely on IOC to interupt and have not had any problems. - Ben On Fri, 11 Jun 2004 15:59:27 -0700, Bob Blick wrote: > > > IIRC on these chips, you can write to the port and it will not reset > > the IOC internal latch values (internal latch not GPIF interupt flag > > or whatever). However, BSF, BCF, ANDWF, etc are all read-modify-write > > instructions that will cause a "read" and reset the IOC latches. So > > you would have to use MOVWF to update your pins without messing up the > > IOC. > > I just doublechecked the data sheet - 12F629 is the same as with the older > chips - either a read or a write to the port will reset it, so if you get > a change as you're writing to the port, you'll miss it. > > Cheerful regards, > > Bob > > > > -- > http://www.piclist.com hint: The list server can filter out subtopics > (like ads or off topics) for you. See http://www.piclist.com/#topics > -- http://www.piclist.com hint: The PICList is archived three different ways. See http://www.piclist.com/#archives for details.