It's a little more complicated than just that, you need a definite period
of time when *all* FETs are off to prevent cross conduction, more like:

______----______----______
_----______----______----_

I would look into some of the FET driver chips available, many of them are
designed to solve that type of problem. (I know it's not what you wanted to
here :-)

The other thought that strikes me is the new motor-control PICs. If memory
serves this is the kind of thing they were discussing at the PIC workshop a
couple months ago. Take a peek at the 18f2331 it's got enhanced motor
control PWM options that do what you're looking for (IIRC).

Denny



> Hi Joe,
> I need 2 identical PWM signals 180 degrees out of phase:
> [view with a fixed-width font]
> ______------______------
> ------______------______
>
> If the pulse width were varied, it would not just be an inverse:
> ______----______----_
> ----______----______-
>
> Thanks for replying though
> --
> --
> Martin Klingensmith
> http://infoarchive.net/
> http://nnytech.net/
>
> Joe Mann wrote:
>
> > Martin,
> >
> > I had a similar problem (needing a 50% duty cycle signal) and received
this
> > and similar approaches from Mike Hawkshaw and other PICList members.
> >
> > On 5/24/04 Mike Hawkshaw wrote:
> > -------------------------------------------------
> > An interesting app note. If you use very fast logic chips (I'm not sure
that
> > it is quite do able with those families at 15MHz) i.e. 74ls or 74vls
are
> > faster I think, then you might just get away with just using a single
> > inverter to give an invert of your clock signal. The last thing you
want in
> > circuits like these is significant clock signal overlap, which might
come
> > from the delay in a single inverter.
> >
> > If the simple inverter is not good enough, try a pair of "exclusive or"
> > gates, feed the clock signal into one input of each, and then tie the
other
> > inputs to ground on one gate and +5V on the other gate. This will give
a
> > complimentary output which should be well matched for overlap. It is
also
> > possible to do this with an or and an and gate in the same way, but
with
> > identical gates on the same chip, you might get better results.
> > --------------------------------------------------
> >
> > The single inverter or the exclusive ORs might be answers for your
problem.
> >
> > Joe, K9HDE
> >
> > --
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>
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