Martin Klingensmith wrote:
>
> each directional pulse from the H bridge=20
> must have the same on-time duration.=20
>=20

Martin,=20

I had a similar problem (needing a 50% duty cycle signal) and received =
this
and similar approaches from Mike Hawkshaw and other PICList members.

On 5/24/04 Mike Hawkshaw wrote:
-------------------------------------------------
An interesting app note. If you use very fast logic chips (I'm not sure =
that
it is quite do able with those families at 15MHz) i.e. 74ls or 74vls are
faster I think, then you might just get away with just using a single
inverter to give an invert of your clock signal. The last thing you want =
in
circuits like these is significant clock signal overlap, which might =
come
from the delay in a single inverter.

If the simple inverter is not good enough, try a pair of "exclusive or"
gates, feed the clock signal into one input of each, and then tie the =
other
inputs to ground on one gate and +5V on the other gate. This will give a
complimentary output which should be well matched for overlap. It is =
also
possible to do this with an or and an and gate in the same way, but with
identical gates on the same chip, you might get better results.=20
--------------------------------------------------

The single inverter or the exclusive ORs might be answers for your =
problem.=20

Joe, K9HDE

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