Hi Tom, You are right about the "glow of dreams" possibly clouding my view, but since this is a one-of-a-kind hobbyist kinda project, being impractical (because of the many division/multiplications/PLL generations of = discrete frequencies to get the desired result) is not a large issue for me. = Being impractical because this or any other technology cannot be made to work obviously is a show stopper.=20 Also what would be of significant concern to me is that the stability, accuracy and low noise characteristics of the original oscillator be = lost. =20 Issues like skewing of digital edge transitions, output being unusable = for use as a receiver local oscillator, digital to sine wave conversion = quality, noisy PLL signal generation or phase noise, etc. are beyond what I comfortably know about electronics. =20 What I know is that I have a 'good' oscillator at 15 MHZ. Its specifications are less than 1 ppb drift per day after 7 days operation. 1. I would like to generate a 10 MHz signal locked to the 15 MHz = "master" for use as a counter timebase. My current counter timebase crystal oscillator drifts about 1 Hz per degree F change. 8-( 2. I would like to provide 40 MHZ and 8050 kHz signals to replace the crystal oscillators in an existing all-band synthesized communications receiver. Today these two oscillators drift about 10 Hz within the = first 2 hours after a cold start and several more HZ if the ambient room = temperature varies between 65 and 80 degrees F. 3. I would like to discipline the 15 MHz "master" oscillator with either = the 1 pps output of a GPS receiver or to WWVB at 60 kHz. In either case a = PLL would provide a control voltage for the unit's electrical frequency = control. 4. I have a VLF upconverter which uses a 4 MHz crystal oscillator. This oscillator also drifts with change in ambient temperature. As an end result (way down the road?) I would like to have a receiver in which all the frequency generation is traceable to the 15 MHz oscillator which is locked to a GPS signal or to WWVB.=20 I will be using HC CMOS chips for the most part. I believe I can build crystal oscillators for most of my required frequencies. I don't know = for sure, but slaving them to the 15 MHz "master" should be do-able. I = assume that the outputs would be usable as receiver LOs. I'm guessing I will = have to build a crystal oscillator and an equivalent PLL oscillator = (74HC4046) and compare them to determine which is best for my application. I believe that I can build circuits that perform the above functions. I suppose that the real question is whether the sum total will deliver the desired results or if there are some hidden, or maybe not so hidden, = gotchas which will make this project, as you say, "impractical in application" = or maybe even DOA.=20 You have assisted me before and I do appreciate the support and = comments. =20 Joe, K9HDE=20 > > Tom wrote: > I reccomand you generate the "digital" signals... 1Hz, 30 and=20 > 60 kHz from the 4 MHz source. CMOS counters are good for this. >=20 > Any signal to be used as an Local Oscillator should be a pure=20 > as possible in many receiver applications. With all the chips=20 > required to to your proposed solution, you might be better=20 > served by just building simple crystal oscillators for the=20 > non-digital requirements. Although your scheme has the glow=20 > of dreams, it is sadly impractical in applicaiton. >=20 > Joe Mann wrote: >=20 > >I am attempting to use the output of a 15 mHz ovenized crystal=20 > >oscillator to generate a 10 mHz sine wave. I believe that=20 > dividing the=20 > >15 mHz by 3 and using the resulting 5 mHz as a reference for=20 > a 10 mHz=20 > >PLL would be the easiest to implement. > > > >Other frequencies that I would like to generate are 1 Hz, 30 kHz, 60=20 > >kHz, 4 mHz, 8050 kHz and 40 MHz. These signals will be used as=20 > >receiver local oscillators, counter time bases, PLL=20 > references, etc. =20 > >Most, if not all, of the PLL outputs will be single output frequency=20 > >circuits. I plan on using 74HC and CD4000 family chips. > > > >I assume conversion of a sine wave to a square wave at the above=20 > >frequencies is a simple task using inverters. Square wave=20 > to sine wave=20 > >conversion probably requires a 50% square wave as input for starters=20 > >and then some 'clean up' using LC tuned circuits. > > > >I assume at some point that I will need to generate 3, 5 and=20 > possibly=20 > >other odd integer divide by circuits. > > > >I came across an "Odd number divide by counters with 50% outputs and=20 > >synchronous clocks" ON Semi app note AND8001/D. > > > > www.onsemi.com/pub/Collateral/AND8001-D.PDF > > > >The first circuit they describe requires a "differential=20 > clock" which=20 > >is depicted as a 1-input AND gate which has 2 outputs. One=20 > output is=20 > >the negative/complement/bar of the other. > > > >I've never seen this symbol before and have been unsuccessful in=20 > >finding one (or how to build one from discretes) on the internet. > > > >Does anyone have any ideas on how to generate a differential clock=20 > >signal from a 15 mHz signal? (Preferably without a division by 2) > > > >Are non-50% duty cycle signals suitable for use as PLL reference=20 > >signals? > > > >Joe, K9HDE > > > >PS http://www.wenzel.com/documents/circuits.html has several unique=20 > >frequency manipulation circuits. -- http://www.piclist.com hint: The PICList is archived three different ways. See http://www.piclist.com/#archives for details.