I reccomand you generate the "digital" signals... 1Hz, 30 and 60 kHz
from the 4 MHz source.
CMOS counters are good for this.

Any signal to be used as an Local Oscillator should be a pure as
possible in many receiver applications.
With all the chips required to to your proposed solution, you might  be
better served by just building
simple crystal oscillators for the non-digital requirements.  Although
your scheme has the glow of dreams,
it is sadly impractical in applicaiton.

Joe Mann wrote:

>I am attempting to use the output of a 15 mHz ovenized crystal oscillator to
>generate a 10 mHz sine wave.  I believe that dividing the 15 mHz by 3 and
>using the resulting 5 mHz as a reference for a 10 mHz PLL would be the
>easiest to implement.
>
>Other frequencies that I would like to generate are 1 Hz, 30 kHz, 60 kHz, 4
>mHz, 8050 kHz and 40 MHz.  These signals will be used as receiver local
>oscillators, counter time bases, PLL references, etc.  Most, if not all, of
>the PLL outputs will be single output frequency circuits.  I plan on using
>74HC and CD4000 family chips.
>
>I assume conversion of a sine wave to a square wave at the above frequencies
>is a simple task using inverters.  Square wave to sine wave conversion
>probably requires a 50% square wave as input for starters and then some
>'clean up' using LC tuned circuits.
>
>I assume at some point that I will need to generate 3, 5 and possibly other
>odd integer divide by circuits.
>
>I came across an "Odd number divide by counters with 50% outputs and
>synchronous clocks" ON Semi app note AND8001/D.
>
> www.onsemi.com/pub/Collateral/AND8001-D.PDF
>
>The first circuit they describe requires a "differential clock" which is
>depicted as a 1-input AND gate which has 2 outputs.  One output is the
>negative/complement/bar of the other.
>
>I've never seen this symbol before and have been unsuccessful in finding one
>(or how to build one from discretes) on the internet.
>
>Does anyone have any ideas on how to generate a differential clock signal
>from a 15 mHz signal?  (Preferably without a division by 2)
>
>Are non-50% duty cycle signals suitable for use as PLL reference signals?
>
>Joe, K9HDE
>
>PS http://www.wenzel.com/documents/circuits.html has several unique
>frequency manipulation circuits.
>
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>

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