On Sun, 9 May 2004, Bob Axtell wrote:

> So you just need 8 bit clocks to receive a byte using the Frame Sync
> and the data to send the byte. Do you need to provide more than 8
> clocks?

The clocks run continuously; I assume they drive the conversions when
you're not clocking data in/out.

> Can the transfer speed be almost any speed, as long as Frame
> Sync is reliable?

The datasheet indicates the allowed clock speeds, and the transfer is
at one of those speeds.

> How about the 8K period? If the master clock is slowed down in
> proportion, can the chip work with 7.5K sample rate without significant
> difference?

I've only used it within spec.

> Well, I would initiate SPI with the clock low, and READIN or SENDOUT the
> data from DR or to DR, with the SPI clock providing the bit clock. The
> ss\ will be inverted to become the Frame Suync Pulse. Wouldn't that work?

That's not going to provide a continuous clock.  I used a 256kHz PWM
off of the PIC to provide the clocks.

--
John W. Temples, III

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