What do you mean by extended I/O space that you can't use I/O opcodes
on?  If I'm thinking of the same I/O space you are, it's because they
managed to pack so much in to the chip, but they are limited by the size
of the instruction word.  So they can only access the first 64
locations, and the rest have to be accessed using the extended I/O
operations.  No biggy.

Just means that instead of
in r16
you have
lds r16

If there's latency coming out of sleep, perhaps it's your oscillator?
I've never had a problem with latency, especially since these chips are
quite a bit faster than your standard pic (can't speak of the 18 series,
though some are on order).

I'm surprised there's a chip out there that doesn't have an ADC.  I
thought every chip since 1998 had an ADC on it.  ;-)


Shawn Wilton
Junior in CpE
MicroBiologist

Phone: (503) 881-2707
Email: shawn@black9.net

http://black9.net


Herbert Graf wrote:
>>What would you consider an annoyance in the AVR arch.?
>
>
> Since AVR is new to me I only have a few to list, so far:
>
> Note these comments are specific to the ATMega162:
>         - interrupt latency, especially coming out of sleep
>         - no A/D on what I consider a pretty high in the scale of things part
>         - "extended" I/O space that you can't use IO opcodes on
>
> Can't think of anything else right now.
>
> One thing I really notice is that the AVR REALLY looks like a PIC that has
> been improved upon, alot of the instructions are very similar to PIC
> instructions. Neat. I'll give it a try, once I come up with a new project.
> Anyone have any ideas? :) TTYL
>
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