>> So in the end bypass caps stabilize your power supply to your
>>chips reducing the amount of noise on those power supply lines.
>>
>> Sprinkle liberally.
>
>What value cap would you use?

In the days of TTL the rule of thumb was a 0.1uF or 0.047uF at every chip.
For CMOS you can get away with smaller values or less capacitors. The cost
of capacitors probably means that there is not a lot to be gained by going
to smaller values unless you are making production runs in the 10 thousands
or more.

I typically work on a 0.047uF to about every 3 chips for normal CMOS logic,
but around a micro and memory where there is continuous clocking then one to
each chip. It also pays to have a larger cap, 10uF or so, one to about 10
chips. On TTL these were typically put at the end of each row of chips where
the row power tracks were split off from the column power tracks.

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