----- Original Message -----
From: "Alan B. Pearce" <A.B.Pearce@RL.AC.UK>
To: <PICLIST@MITVMA.MIT.EDU>
Sent: Monday, April 05, 2004 9:16 AM
Subject: Re: [PIC]:ISR and TMR0


> > However, adding in additional code inside
> >the ISR, affects how often it enters into the ISR, granted
> >only by uS, but then adjusting how often some other registers
> >get reset/reloaded based on whats going on inside the ISR,
> >it can add milliseconds to these reloads.
>
> I suspect that what you are seeing is an accumulation of timing errors
that
> occur when reloading the timer. If you reload the timer by adding the
> negative of the reload value to the value currently in the timer than you
> should have the correct interval every time.

Actually, this is only true if you have a 1:1 prescaler, and you also have
to adjust the value you add by 2 to account for the fact that TMR0 'freezes'
for 2 clocks when you update it.


If you want an interrupt every N clocks, then inside the TMR0 interrupt
handler just:

    movlw    254-N
    addwf    TMR0

Bob Ammerman
RAm Systems

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