>-----Original Message-----
>From: Jinx [mailto:joecolquitt@CLEAR.NET.NZ]
>Sent: 11 March 2004 02:36
>To: PICLIST@MITVMA.MIT.EDU
>Subject: Re: [PIC:] My first program, 18F452, please critique
>
>
>> It doesn't get any clearer than those scope results. If I manipulate
>> LATD instead of PORTD is it possible to get the same problems ?
>
>The relationship between PORT TRIS and LAT can take a little
>getting to grips with. This is how I understand it, although I
>have to admit not really getting involved with LAT much. If
>anyone has anything to add or correct, please do
>
>=============
>
>The last value written to PORT is in LAT. eg LATD holds the
>contents that are to be written out if a pin is configured as an output
>

This is not quite correct.  All writes to a port must by definition go to
the data latch (LATx), even if you are actually writing to PORTx i.e.
although you can read the pin states via PORTx you always change their state
through LATx.  The big problem comes from writing to PORTx, whereby the pins
are read, the value modified and then written back to the data latch.

The older parts did not have to capability to read the data latches
directly, only the output pins which as many people have discovered isn't
always the same thing.  With the introduction of the LATx SFR's, R-M-W
problems on the ports are pretty much a thing of the past.  You can set or
clear a bit in the LATx register, safe in the knowledge that no other bits
will be affected, even if their associated pins are configured as inputs.

The general rule to using ports on an 18F part is to write to LATx and read
from PORTx.  This way the values written to the data latch can be relied on
to stay the way they are, even if TRISx is being manipulated.

The LATx SFR's are probably one of the most useful additions to the 18F
series of devices if bit bashing is your thing.

Regards

Mike





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