Jim Robertson wrote: > > > MOVE C, src. ;Move Register Bit to Carry > > > JUMP C/NC > > > > > Both these are single clock cycle instructions unless the > > > JUMP is a long jump. Looks to me that the PIC loses again > > > on the clock cycle count at least. > > > > PIC wins at byte count, > > Off hand I cannot see how. Can you demonstrate this? Sure, Jim. BTFSS/C REG,BIT GOTO LABEL 28 bits (or 24 bits, since this code also works on the 12-bit PICs), versus 32 bits for the MAXQ. > > PIC wins at not corrupting the carry > > Yes, this is a huge advantage to the PIC and a real downer for the > MAXQ architecture. Of course, this reminds me of your ASL example > corrupting the WREG. Yeah, they do seem similar... But there are differences that I think are significant. The PIC's accumulator (W) is a source operand for every arithmetic operation, so corrupting it during an arithmetic operation like Arithmetic Right Shift isn't unexpected. The Carry flag is also primarily an arithmetic function, though, so it's "unnatural" for it to be corrupted during a non-arithmetic, bit-oriented logical operation. Also, the accumulator-corruption happens while CHANGING the contents of PIC registers; the carry-corruption happens while merely EXAMINING the contents of MAXQ registers. > > 196 cycles [versus 296] while only adding 12 words of > > code space: > > That's a 120% increase. That "seems like a significant increase to > me..." Apples and oranges. The "6 vs 10" comparison was between shorter/faster code and longer/slower code; 6 was the clear winner by either metric. In this case, though, the shorter code is also slower, so the "winner" depends only on your judging criterion. I interpreted the "contest" to be all about speed, not size, so faster code wins. I might have misunderstood your intent. > I could fine no reference to maximum clock .... > Looking at Maxim's 8051 core, they do have a 33MHz single clock per > instruction cycle chip. Quite a feat given that the 8051 was > originally 12 clocks per instruction cycle. Actually, that's not too unusual these days; we've been making 48 MHz (mostly-)single-cycle 8051s for the last few years. > Anyway, with all this talk on the PICLIST, it will be an > interesting intellectual exercise (at least) watching how this > architecture is implemented and if it succeeds or not. Agreed. > The method of bit I/O is somewhat off putting. ... and I can agree to that, too. Can't wait to see what Maxim will charge for these chips... And what their development tools will look like and cost, what the chip's I/O specs will be, what peripheral interfaces will be included, how many timers/counters they'll have, how their interrupt structure will work, what their operating voltage range will be, etc. -Andy === Andrew Warren -- aiw@cypress.com === Principal Design Engineer === Cypress Semiconductor Corporation === === Opinions expressed above do not === necessarily represent those of === Cypress Semiconductor Corporation -- http://www.piclist.com hint: The PICList is archived three different ways. See http://www.piclist.com/#archives for details.