>Jim Robertson wrote: > > > The difference between their 40 cycles and the above 24 cycles is only > > 4 PIC instructions. > > Jim: > > 24 is 60 percent of 40. Seems like a significant savings to > me... Yes, Andy, but the context of my remark was that people were comparing 6 PIC instructions cycles against the 40 PIC clock cycles quoted by Maxim and this is a difference of 85% The fact is that aspersions were been made against maxim due to this incorrect reading of the MAXQ document. That is why I said the bit about 4 instructions, it helps put it back in context. While I have replied to some of your points below, Please understand that I am NOT interested in advocating the MAXQ over the PIC, my intent is to show that there were mistakes made by piclister's, as you have conceded, and there were some rather unfair comments made about the accuracy of the MAXQ document. "Scum marketing" comes to mind. > Also, a LOGICAL right-shift still takes 24 cycles on the PIC, > but (if I'm reading the instruction set properly, and the only > multi-bit shifts are arithemetic) it would double the execution > time and code space requirements on the MAXQ20. Yes, Agreed. Doubled but still less clock cycles than a PIC. > > My EXPECTATION would be that the code they used (not shown) is > > designed to use the same sort of resources on each micro. That is, > > not having to use additional registers etc as there is no such > > requirement to do so with the MAXQ architecture > > .... > > [with that assumption,] their claim of 40 clock Cycles LOOKS > > CORRECT. > > > I don't think their code took 40 cycles because of any > requirement to use the same resources on each micro; I think > they just weren't familiar enough with the PIC instruction set > to figure out how to do it in 24. Maybe, maybe not. The point still remains that there appears to be no evidence that maxim set out to misled. They may have done a poor job outlining their intent or just coded poorly. Again, the issue is the way people on the PICLIST reacted when it was they who were making an error comparing instruction cycles against clock cycles which somewhat amplified 4X any poor coding. > > surely you would then convert "Bytes" into the MAXQ's 16-bit > > instruction word also, right? > > Yes, of course you are correct. My mistake. > > > > > MOVE C, src. ;Move Register Bit to Carry > > JUMP C/NC > > > Both these are single clock cycle instructions unless the JUMP is > > a long jump. Looks to me that the PIC loses again on the clock > > cycle count at least. > > PIC wins at byte count, Off hand I cannot see how. Can you demonstrate this? > PIC wins at not corrupting the carry Yes, this is a huge advantage to the PIC and a real downer for the MAXQ architecture. Of course, this reminds me of your ASL example corrupting the WREG. 40 Cycles seems to be on the money when protecting resources is an issue. Granted, in one case you have an option, the other you don't... > > The example below has little, if any, fat and I count 296 clock > > cycles. snip... > Here's mine; it takes 196 cycles while only adding 12 words of > code space: That's a 120% increase. That "seems like a significant increase to me..." snip... Ok, many people have hammered me using straight line code. It was remiss of me not to consider the possibility of using straight line code. My priority was to show how maxim reached their benchmark figure and they did so using the most likely trade-off between size and speed and (presumably) they were consistent with the looped algorithm across all micros. Naturally, you could also use straight line code for all the other Micros though clearly the gains for the PIC are greater than those for the MAXQ as the PIC can set and reset the clock with one instruction verses the MAXQ's 2) and the MAXQ's advantageous "DNJZ" is removed. As it is, this benchmark was the only benchmark where the PIC had the same number of instructions words. Even when you trade that off to lower the cycle count, it still has many more cycles than the MAXQ. (And we have yet to see a revised, straight line MAXQ benchmark.) > By the way... Looking over the MAXQ info, I don't see a Maximum > CPU Frequency spec. Am I just overlooking it, or are they waiting > to publish that number until after they actually have silicon? Just out of curiosity I went looking myself. I could fine no reference to maximum clock (I could fine no other reference to the MAXQ anywhere on the MAXIM-IC web site.) Looking at Maxim's 8051 core, they do have a 33MHz single clock per instruction cycle chip. Quite a feat given that the 8051 was originally 12 clocks per instruction cycle. Anyway, with all this talk on the PICLIST, it will be an interesting intellectual exercise (at least) watching how this architecture is implemented and if it succeeds or not. The method of bit I/O is somewhat off putting. Regards, Jim > -Andy > >=== Andrew Warren -- aiw@cypress.com >=== Principal Design Engineer >=== Cypress Semiconductor Corporation >=== >=== Opinions expressed above do not >=== necessarily represent those of >=== Cypress Semiconductor Corporation > -- http://www.piclist.com hint: The PICList is archived three different ways. See http://www.piclist.com/#archives for details.