Michael Rigby-Jones wrote:


> > Shift a 16 bit value right two bits, allegedly the PIC takes 40
> > cycles!
> >
> > clrc                    ;1
> > rrf  val+1,f    ;1
> > rrf  val,f              ;1
> > clrc                    ;1
> > rrf  val+1,f    ;1
> > rrf  val,f              ;1
> >
> > I make that 6 cycles + a couple for initial bank setting if we are
> > being fussy.


Andy Warren replied:



>     No, that's not what they wanted... They're doing an ARITHMETIC
>     right shift, so the MSB gets preserved rather than being cleared
>     to 0.  Also, they explicitly say no bank switching was required.
>
>     Still only takes 6 cycles, though:
>
>         RLF HI,W
>         RRF HI
>         RRF LO
>
>         RLF HI,W
>         RRF HI
>         RRF LO

Hello All,

As has been pointed out,  the MAXQ document is comparing CLOCK CYCLES and
although the document is ambiguous in places, it is still quite clear
overall that this is
the case.

Clock cycles are 4X (or 8X) instruction words on a PIC so really the above
takes 24 clock
cycles,  not 6.

The difference between their 40 cycles and the above 24 cycles is only 4
PIC instructions.

My EXPECTATION would be that the code they used (not shown) is designed to
use the same
sort of resources on each micro. That is, not having to use additional
registers etc as there is no
such requirement to do so with the MAXQ architecture (I am presuming this
based on what
information is available at this time.)


Possible PIC example:

         BCF STATUS,C
         RRF HI
         RRF LOW
         BTFSC HI,6
         BSF HI,7

         BCF STATUS,C
         RRF HI
         RRF LOW
         BTFSC HI,6
         BSF HI,7

This equals 40 clock cycles without the use of the WREG.

The bottom line to me seems that only valid criticism of the MAXQ claims
with this example
code comparison is that requirements of no extra registers etc is not well
qualified and the
actual code they used is not presented. Otherwise their claim of 40 clock
Cycles LOOKS
CORRECT.

>     Interestingly, they've chosen to use "Bytes" as the unit of code
>     space in all their comparisons.  If you do the natural thing and
>     convert from bytes to 14-bit PIC instruction words, you'll
>     "discover" (as though you could have had any doubt) that the PIC
>     code is always shorter than the MAXQ code.

Well, surely you would then convert "Bytes" into the MAXQ's 16-bit
instruction word also,
right?

This is NOT favorable to the PIC as the number of PIC instruction words is MORE
that 2X  the number of bytes specified as the bytes have been PACKED in all
the examples
given.

Refer to Memory copy (MemCpy64)

The total instruction words for a PIC was 12 words. The number of bytes in
the table is 21
(12*14) (bits) / 8 and not 24 bytes.

The document is consistent in this and therefore FAVORS the PIC16 whenever
bytes are
counted.

So I say Andy is right, it would be more "natural" to count instruction
words, but then we would
see that the MAXQ code is usually, but not always, shorter than the PIC code.


>     Also interesting was the absence of any example that involved
>     reading I/O pins.

Looking at the instruction set it would appear that a I/O Bit Read with
conditional branch would
be coded something like this.

         MOVE C, src.<b>       ;Move Register Bit to Carry
         JUMP C/NC

Both these are single clock cycle instructions unless the JUMP is a long
jump. Looks to me
that the PIC loses again on the clock cycle count at least.


===================================================================

COMMENT

While it appears agreeable to me that parts of the Maxim MAXQ document may
be flawed,
my reading of it is that some of the "rebuttal" spread throughout this
thread (with all its
various tags), is far more so and seems to be more of an emotional  PIC
"Fanboy" flavor than
anything else.

Who would consider their choice of micro based on the quality of
information posted on the
piclist throughout this thread? You would have to be nuts...

Yes it DOES take around 296 clock cycles to bit bang a 8 bit value to an
I/O pin SPI style.
If anyone wants to elude that this is a ridiculous claim I await your code
to prove otherwise!!!

The example below has little, if any, fat and I count 296 clock cycles.

                MOVLW  8
                MOVWF  COUNT

MYLOOP
                BCF  DATABIT
                RRF  BARREL
                SKPNC
                BSF  DATABIT
                BSF  CLKBIT
                BCF  CLKBIT
                DECFSZ  COUNT
                GOTO  MYLOOP



Naturally, I am open to be shown how and where I may be wrong with the above
analysis.

Regards,

Jim Robertson
NEWFOUND ELECTRONICS

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