Hi.
Just saw this...

> > > While single stepping thru the code, I have both the TRIS and PORT
> > > registers in the view window.  However, I notice when I simply do a
> > > movlw 0x04 movwf PORTB
> > >
> > > I don't always see it update on the view window, and I am
> > > following with a
> > > banksel TRISB
> > > movlw 0x00
> > > movwf TRISB
> > >
> > > I then sometimes see a change in PORTB.  Since the TRIS
> > > and DATA are both registers, it wouldn't seem correct that the
> > > read back of  the value stored in the PORT register is affected
> > > by the TRIS value.

Note that the *reading* from the PORT reg, reads whatever the level
is on the *pin*, not the PORT reg itself (or actualy the latch reg, which
on the 18-series is readable through the LAT reg, b.t.w).

Now, if the pins are set to input, the value in the latch register (written
by writing to the PORT reg) does not have to be the same as when
reading from the PORT reg. I'd expect that you need a "stimilus file"
to set the levels on input pins or they'll defualt to either 0 or 1.

When you set the pin to *output* (using TRIS), a read from the PORT
reg will *then* read the value in the latch register, which is correct.

And I'd expect the MPSIM to correctly simulate this...

Jan-Erik.

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