>At 09:42 AM 2/26/2004 +0000, Mike Rigby-Jones wrote:
>
>>The benchmarks are also mighty suspect to say the least.  For
>>starters no source code is shown for most of them, and the
>>cycle count for the PIC's is frankly ludicrous e.g.
>>
>>Shift a 16 bit value right two bits, allegedly the PIC takes
>>40 cycles!
>>
>>clrc            ;1
>>rrf  val+1,f    ;1
>>rrf  val,f      ;1
>>clrc            ;1
>>rrf  val+1,f    ;1
>>rrf  val,f      ;1
>>
>>I make that 6 cycles + a couple for initial bank setting if we
>>are being fussy.


>-----Original Message-----
>From: Spehro Pefhany [mailto:speff@INTERLOG.COM]
>
>I think they are multiplying machine cycles by 4 to get Fosc
>cycles in PIC parlance. Make more sense?

OK, makes a little more sense, although the numbers are still out after
multplying by 4.  It would also explain why they didn't compare to the 18F
with it's 4x PLL multiplier!

Regards

Mike




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