On Mon, 16 Feb 2004, Robert James Kaes wrote:

> Hello,
> I seem to be having a problem doing a computed goto with a 18f258.
> I'm basically trying to make a state machine, but only the first two
> states are working, and I use that term loosely.
>
> I'm using the following code to generate the state-machine run loop.
> The "curr_state" variable holds the current state number.  I've made
> this a macro so that the GOTOs can be generated automatically.  In
> my test code, the "states" is set to 3 (so, labels state0, state1, and
> state2.)
>
>
> run_state_machine       macro   states
>         movlw   UPPER(state0)   ; make sure the upper bytes of the PC
>         movwf   PCLATU          ; register are defined to the
>         beginning
>         movlw   HIGH(state0)    ; of the state machine goto list
>         movwf   PCLATH
>
>         banksel curr_state
>         rlncf   curr_state, W   ; double because gotos are two words long
>         addwf   PCL, F
>
>         local index = 0
>         while index < states
>         goto    state#v(index)
> index = index + 1
>         endw
>         endm
>
>
> Does anyone see what I'm doing wrong with this code?  When I set
> "curr_state" to 2, it should vector to the third GOTO, but that does
> not happen.

Change your GOTO's to BRA's if you can. You'll still need the RLNCF
because (IMO) of a design flaw in the 18f architecture. Whenever you add a
constant to PCL you gotta multiply it by 2 first. E.g:


       ADDWF  PCL,F
       bra    W_was_0     ; hit this branch if W was 0
       bra    W_was_2     ; ...
       bra    W_was_4


If you have to use goto's instead of bra's, then you'll need to multiply
your state by 4.

BTW, the reason for this "design flaw" is because the program memory reads
and writes are byte addressable. However, instruction fetches are word
addressable. The chip probably uses the same decoder for instruction
fetches and program memory reads/writes. I have no idea why they didn't
shift the instruction fetch addresses right one bit. Now we're stuck with
byte addressed tables only capable of spanning 128 words instead of 256
words like in the 14-bit core.

Scott

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