Olin Lathrop wrote:

> ...Then I tried something that DID make it work...
> ...Can you guess what it was?...

1) You tried a trapezoidal line driver and line driver/receiver on the
SCLK/SDATA lines (respectively)?

Like we say with the weather, "It's not the heat it's the humidity."
In electronics: "It's not the frequency, it's the edge transitions."

Hmm, I do not see any *explicit* rise/fall time restrictions on SCLK/SDATA
in the programming specification I'm looking at right now, but I do see a
capacitive loading specification on SDATA of 50 pF max of capacitance.


Probing questions:

1)   Did you find significant ringing on Vpp that caused Vpp to dip below
the VIHH spec on the down swing of the ringing -- thus causing programming
mode to inadvertently exit?

2)   Is the problem related to the target chip's package parasitic
inductance?


I'm enjoying this challenge, we should do more of these on the PICLIST.

I think you are going to hit us all with something good on April 1st. I will
be ready. :)

Best regards,

Ken Pergola

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