> Well, CPLDs and FPGAs are looking pretty flipping cool
>
> I'm thinking back to projects that used heaps of 74 for I/O control
> or had 1/2 dozen PIC+SX, basically as smart steering logic
>
> Something I'll be looking into

        CPLDs/FPGAs are great for taking over tasks that don't require that much
logic, but that need to go fast, or require a large amount of I/O. For
example my logic analyzer project
(http://repatch.dyndns.org:8383/pic_stuff/logan) uses a CPLD to address an
SRAM, and properly clock the enable lines, while the PIC is used to command
the CPLD on the operation it is to perform. While it COULD have been done
with a PIC alone it would have been MUCH more painful. TTYL

----------------------------------
Herbert's PIC Stuff:
http://repatch.dyndns.org:8383/pic_stuff/

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