---- START NEW MESSAGE --- Received: from cherry.ease.lsoft.com [209.119.0.109] by dpmail10.doteasy.com with ESMTP (SMTPD32-8.05) id AC5468D40116; Sun, 01 Feb 2004 12:06:44 -0800 Received: from PEAR.EASE.LSOFT.COM (209.119.0.19) by cherry.ease.lsoft.com (LSMTP for Digital Unix v1.1b) with SMTP id <15.00CC7FD9@cherry.ease.lsoft.com>; 1 Feb 2004 15:06:39 -0500 Received: from MITVMA.MIT.EDU by MITVMA.MIT.EDU (LISTSERV-TCP/IP release 1.8e) with spool id 2533 for PICLIST@MITVMA.MIT.EDU; Sun, 1 Feb 2004 15:06:32 -0500 Received: from MITVMA (NJE origin SMTP@MITVMA) by MITVMA.MIT.EDU (LMail V1.2d/1.8d) with BSMTP id 3161; Sun, 1 Feb 2004 15:06:24 -0500 Received: from cassiopeia.email.starband.net [148.78.247.122] by mitvma.mit.edu (IBM VM SMTP Level 430) via TCP with ESMTP ; Sun, 01 Feb 2004 15:06:23 EST X-Comment: mitvma.mit.edu: Mail was sent by cassiopeia.email.starband.net Received: from pacific.net (vsat-148-63-152-126.c189.t7.mrt.starband.net [148.63.152.126]) by cassiopeia.email.starband.net (8.12.10/8.12.9) with ESMTP id i0V7ILZs029167 for ; Sat, 31 Jan 2004 02:18:32 -0500 User-Agent: Mozilla/5.0 (Windows; U; Win98; en-US; rv:1.4) Gecko/20030624 Netscape/7.1 (ax) X-Accept-Language: en-us, en MIME-Version: 1.0 References: <200401310502.i0V52FN9009363@mailfilter2.pacific.net> Content-Type: text/plain; charset=us-ascii; format=flowed Content-Transfer-Encoding: 7bit Message-ID: <401B589B.6060007@pacific.net> Date: Fri, 30 Jan 2004 23:26:19 -0800 Reply-To: pic microcontroller discussion list Sender: pic microcontroller discussion list From: Brooke Clarke Subject: [PIC]: Re: 12F675 To: PICLIST@MITVMA.MIT.EDU In-Reply-To: <200401310502.i0V52FN9009363@mailfilter2.pacific.net> Precedence: list X-RCPT-TO: Status: U X-UIDL: 371856769 Hi: That is not quite correct and is one of my pet peeves. Pin 4 is can only be an Input pin (NOT an Output pin i.e.not an I/O pin) when MCLR is configured internally. This means that the 12F675 uses 2 pins for power and there are 5 possible I/O pins and one Input only pin. The data sheet is in error on this point. Have Fun, Brooke Clarke, N6GCE http://www.PRC68.com >Date: Fri, 30 Jan 2004 23:27:02 -0500 >From: Matthew Miller >Subject: Re: 12F675 > >Hello, > >On Thu, Jan 29, 2004 at 12:20:14PM -0500, NEWZED@AOL.COM wrote: > > >>Second posting - don't think the first one made it. >> >>We are looking at the 12F675 and after reading the data sheet understand most >>of it. I have one question - pin 4 is indicated as an I/O and MCLR. My >>understanding is the MCLR must always be pulled high for normal operation. >> >>How can this be accomplished and the pin still be used as an I/O. Can >>someone enlighten me, please. >> >> > >Section 9.1 of the datasheet show the uses of the bits in the configuration >byte. If the bit MCLRE is set to 0 then the pin can be used for general purpose >I/O, otherwise the pin can be used as !MCLR. How this those bits in the CONFIG >byte are set depends on what assembler or compiler you use. > >Take care, Matthew. > >-- >"There is nothing so strong as gentleness, and there is nothing so gentle >as real strength." -- St. Francis de Sales > > > > -- http://www.piclist.com hint: PICList Posts must start with ONE topic: [PIC]:,[SX]:,[AVR]: ->uP ONLY! [EE]:,[OT]: ->Other [BUY]:,[AD]: ->Ads .