Of course, as you know, your choice would be limited by whether you can do
low side switching or high side switching in the first place. After that is
the availability of good P channel FETs to do high side switching from logic
level gate voltages. P channels, typically, have a higher gate capacitance
and a higher RDSon for a given Idrain. Ideally, low side switching using a N
channel logic level FET serves one best. If that is not an option, you can
get FET drivers with built in charge pump and use a N channel FET for high
side switching. I would personally use a logic level P channel FET for high
side switching as the last option.
Madhu

>-----Original Message-----
>This is mostly unrelated to the previous posts on this thread, but the
>question occured to me as I was reading them...
>
>P-channel vs. N-channel FETS: given the ability of PIC output
>ports to drive
>either a high or low logic level, to apply to the FET's gate, are there any
>design considerations that should dictate choosing one over the other
>(that's P vs N- channel)?  I'm thinking primarily w.r.t. power-up
>conditions, polarities, etc.
>
>Jim

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