Hi,

I had experiment with PIC's USART in recent weeks and now I get somthing
that is working.
Anyway I still have some question here.

When a byte of data is received, what is the time until the next byte of
data come in again? I am using a 9600bps buadrate. I asume that for a bit of
data transfer, it take 1/9600 sec. So for receive a byte of data +
start/stop bits, it is 10/9600 sec.

Then what is the instruction cycle before next byte of data received. I
asume an instruction cycle take 4 * 1/16MHz (I am using 16MHz for Fosc). So
is that meant the instruction cycle we have to manipulate the data just
received is (10/9600) / (1/16*10^6), or (10/9600) * 16* 10^6 ?

Then does the BRGH setting have an effect to above calculation?

Please correct me if I am wrong.
Thanks in advance.

WH Tan

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