Pretty much agree, Olin...

Olin Lathrop wrote:

> Bob Axtell wrote:
>
>>To do this well, the PIC would have to be almost dedicated to ONLY
>>servicing the I2C Master and doing nothing else.
>
>
> That depends.  The MSSP in slave mode can do clock stretch on a read, so
> there is a means of flow control in that direction.  Unfortunately Microchip
> didn't implement clock stretch for writes, although there are other ways to
> deal with this.  Data coming into the slave IIC port is not that much
> different than data coming into the UART.  Eventually you still have to
> handle it at the speed it decides to come at.

I've ALWAYS been disappointed with MC on not implementing a PROPER I2C
port. I THINK they didn't want to pay the Phillips royalty.

More serious with the MSSP unit is that it mixes I2C and SPI. The SPI
portion of the MSSP is a wonderful piece of hardware, and I love it.
There is no real speed restriction in SPI slave mode; when you receive
a frame, you get an interrupt, then go read it. But, the I2C...

Really, look at it; the I2C portion of MSSP is really limp. First, you
can do either I2C OR SPI on the same chip, not both. Then, you get an
interrupt on START and STOP, and the ACK is OK- fine; but you don't get
much more than that. Everything else you do has to be heavily "tinkered
with".

A proper I2C hardware engine would operate seamlessly. The slave engine
would know when a start bit is expected, and properly turn on WHEN THE
ADDRESS MATCHES and proceed to accept data, with a status byte somewhere
keeping up with what kind of data was coming in. Even the 7-bit/10-bit
address could be handled. It would then be reset when the STOP bit
occurred. Even an 8-byte I/O FIFO would be nice...

BTW, Happy New Year! to Olin, Wouter, James, and everyone! Its fun
sparring with you guys; you are a tough act to follow...

--Bob



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                Bob Axtell
        PIC Hardware & Firmware Dev
          http://beam.to/baxtell
              1-520-219-2363

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