Hopkins <PICLIST@mitvma.mit.edu> wrote:

> 1 cycle shown in the section 29 instruction set of the Mid Range
> Reference manual

    Yes... In general, it's true that ADDWF takes one cycle.
    However, an ADDWF (or any other write instruction) with PCL as
    its destination requires two cycles.

    -Andy

=== Andrew Warren -- aiw@cypress.com
=== Principal Design Engineer
=== Cypress Semiconductor Corporation
===
=== Opinions expressed above do not
=== necessarily represent those of
=== Cypress Semiconductor Corporation

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