Wouter van Ooijen wrote:
> There was actual silicon to play with.

Just out of curiosity, which parts did they let you see?

> But note that
> the DSP-part of the chip is based on 16-bit integers, not on 32 bits
> like most DSPs I know.

This is meant to be a low end DSP.  Other low end DSPs are also 16 bits.
Note that the two DSP accumulators are 40 bits wide.  The architecture
assumes your input and output values won't need more than 16 bits, but
provides for much wider internal intermediate values.  16 bits is adequate
for the majority of convolution coeficients and input/output sample data
points.

> Does someone have any idea what impact that
> will have, like a lower signal-to-noise ratio?

Very little, because the real signal to noise limit comes from the external
analog electronics, not the 16 bits for expressing individual data points.
Note that a full 16 bits implies 96dB signal to noise ratio.  Try finding an
A/D that can do that.

> Another funny note: the SCL and SDA roles (default RB6/RB7)
> can be assigned to three other pairs of pins by changing the fuses.

I think you meant to say PGD and PGC?  SCL/SDA are the normal names for IIC
bus lines.  In any case the PGD/PGC programming lines can not be remapped.
I think you are confusing these with EMUD/EMUC which are the ICD2 debugger
lines.  These CAN be remapped, but all the support isn't really there yet
(guess how I found that out).


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